The QDR co-development team, a consortium of large memory-chip makers, released specifications for the next generation of Quad Data Rate and Double Data Rate SRAM architectures on Monday.
The announcement came as one consortium member, Boise, Idaho-based Micron Technology Inc., released engineering samples of the new chips.
The consortium, whose other members include Cypress Semiconductor Corp., Integrated Device Technology Inc., NEC Corp. and Samsung Electronics Co., said the new chips offer more speed and use up less power than their predecessors. (Hitachi Ltd., which signed a letter of intent to join the consortium last month, was also part of the announcement.)
QDRII and DDRII devices operate at speeds of up to 333 MHz, compared with the 200 MHz QDR and DDR devices.
“This is a significant performance improvement,” said Hiroyuki Goto, senior manager of engineering and marketing for NEC’s memory products group. Goto added the QDRII and DDRII products require 1.8 volts or power compared to the 2.5 volts required by QDR and DDR chips.
QDRII and DDRII devices, expected to go to market in late 2002, are designed for high-end routers or switches. Mario Martinez, director of strategic marketing for Cypress Semiconductor, said the devices allow next generation OC-192 and OC-768 networking systems to reach up to 36 gbps memory bandwidth.
“This is a very good evolutionary step in the right direction,” said John Metz, principal analyst for Harvard, Mass.-based research firm Metz International Ltd. “Once you get more efficient memory, you can store more in fewer chips.
“OEMs now look at chip vendors and say ‘Show me how much memory you use.'”
Metz said QDRII and DDRII devices look to fare well in the “three-P test,” increasing the level of performance while reducing the amount of power required. The third “P”, pins used, stays constant as the consortium aimed to maintain backward compatibility with QDR and DDR chips, according to Martinez.
“Basically, (vendors) can design a board that can interchange between QDRII and QDR, but you have to ensure in the hardware that you’re able to support both,” he said.
The Micron samples made available Monday cover the entire family of 18 megabit QDR and 18 megabit DDR SRAM devices. The co-development team has a standing policy of releasing specifications for new chip architectures as soon as one of its members has produced working samples.
“The strategy behind a dual-prong approach is to give credibility to the announcement,” Martinez said. Metz added this approach allows vendors using memory chips to design their product around the new devices.
Consortium members declined to give price estimates for the new chips, saying only that the cost of the chips will be market driven.
