IT industry aims PCI Express at enterprise workloads

SAN FRANCISCO – Advanced Micro Devices recently said rival chipmaker Intel’s plan to enhance PCI Express technology to address performance requirements from compute-intensive applications won’t make a difference

“It’s like having a Maserati out on the expressway at rush hour,” said John Fruehe, worldwide business development manager for AMD Opteron, who spoke to Computing Canada following Intel’s announcement that it and other vendors are working on the next generation of the PCI Express standard.

Pat Gelsinger, Intel’s senior vice-president and general manger of the digital enterprise group, made the announcement at a keynote address to thousands of developers attending the Intel Developer’s Forum (IDF) here. The proposal, codenamed “Geneseo,” describes enhancements that will enable faster connectivity between the processor and application accelerators. Improvements to the technology will allow it to better address the performance requ irements of certain applications that use visualization, math and physics and content processing usage models. These include weather modelling, data-intensive financial applications and encryption and decryption of communications infrastructure data.

Intel first brought PCI Express technology to the market with the launch of its 900-series chipsets in 2004. But the emergence of encryption, visualization and XML is driving new requirements from server platforms. IBM is co-founding the proposal. In a panel discussion following the keynote, Tom Bradicich, CTO, System X and BladeCenter Servers at IBM, likened the relationship of the processor to application accelerators to moving into a neighbourhood and wanting to be close to shopping, for example.

“If you’d like to live near shopping and you needed intimacy with other I/O accelerators or if you want some remote memory application, then that makes a lot of sense,” Bradicich said. “You want to be closer to your work or school. It can’t be possible to be closer to both.”

But AMD’s Fruehe said this doesn’t address the fundamental problem of Intel’s architectural design, which sends data outside of the processor through the front side bus to access the memory controller. This creates a bottleneck because there are four cores (in a quad core processor) choking up the front side bus, said Fruehe.

“This negates any benefits on the PCI express bus,” he said.

AMD’s processors, on the other hand, allow data to flow from one core to another without leaving the chip, which uses less bandwidth and improves the processor’s performance, said Fruehe.

Geneseo is part of an ongoing plan that Intel shares with IBM and other industry vendors to create an open-standards-based interface for the computer industry.

To that end, Gelsinger announced at the conference that Intel will release a whitepaper detailing the next generation of instruction set extensions that will be part of its 45 nanometre products. Intel also announced that the 45 nm processor will be a part of the Nehalem new microarchitecture that is scheduled for release in 2008.

In a Q&A session following his keynote, Gelsinger said open standards benefit the industry.

“We need to be much more open to allow them to do that,” he said. “As a consequence, the competition will see that as well.”

Fruehe, however, said Intel’s approach to open standards doesn’t really benefit anyone but Intel, because it locks them into its platform.

“Intel has a long history of finding ways to block AMD out of the bus,” he said. AMD recently launched the Torrenza strategy, which focuses on creating an open x86 platform.

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Jim Love, Chief Content Officer, IT World Canada

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