Intel Corp. on Tuesday said it has formally shifted its traditional focus on the clock speed of microprocessors to a product development strategy centered around the performance per watt of each CPU.
Speaking to thousands of hardware and software firms attending its Intel Developer Forum
(IDF) this week, chief executive Paul Otellini confirmed widespread expectations that the company is combining elements of its NetBurst architecture with that of its mobile Pentium products to deliver a consistent, power-optimized platform for developers.
Intel introduced Netburst five years ago to boost the video, multimedia, 3-D imaging and encryption capabilities in its Pentium 4 desktop and Xeon server products. Power consumption concerns in NetBurst, however, have led Intel to incorporate more of the Pentium M architecture into its forthcoming desktop chip, code-named Conroe, the Woodcrest server chip as well as the forthcoming mobile chip, Merom.
Otellini said the architectural changes, along with the advent of Intel’s multi-core processor strategy, would significantly improve the ability of CIOs and IT managers to spend less time on maintenance of their IT architecture. Multi-core refers to Intel’s plans to include two or more “brains” on a chip that could split larger workloads. The company plans to launch its first dual-core desktop processor, code-named Yonah, in the first half of next year.
“Performance per watt has always been essential in desktops and servers, but now we’re seeing situations where power is limiting the kinds of devices you can build,” Otellini said, predicting Intel’s next-generation products would find their way into fanless desktops and ultra-dense server environments. “You’ll be able to avoid the power penalties you get with a gigahertz (oriented) approach.”
Otellini promised that Merom – which was used in a notebook, which ran his keynote presentation – would see a threefold improvement in performance per watt over Banias, the mobile processor Intel introduced in 2003. Conroe, meanwhile, will enjoy a fivefold improvement in performance per watt over its predecessor, Northwood, will the Woodcrest server chip will see a threefold improvement over Nocona. By the end of the decade, Otellini added, Intel products will offer a tenfold improvement in performance per watt.
Intel’s strategy was immediately endorsed by the world’s largest search engine. Otelini’s keynote included an appearance by Google fellow Urs Hölzle, who said increased traffic on the company’s Web site has forced the company to get smart about breaking compute requirements into componentized, parallel workloads.
“Just adding CPUs doesn’t really help us, though,” Hölzle said. “If you do the math, the cost of the power over four years is equal to half the cost of your hardware. Over time, you end up paying more money to the electricity company than you do on your hardware.”
Dual-core CPUs will address that problem, Hölzle added, as will Intel’s plan to squeeze additional cores into its chips. Otellini said there are at least 10 projects within Intel’s R&D labs that involve four or more cores.
Intel’s plans for the enterprise include embedding virtualization, management and security technologies deeper into its microchips. Steve Ward, chief executive of Lenovo Corp., demonstrated systems using Intel’s Active Management Technology (iAMT) that could allow an IT manager to set up a PC for a new employee with the machine turned off. A simulation showed how an IT manager console that could remotely assign a network ID, run diagnostics and load a new image onto the PC. A Lenovo product called Antidote Delivery Manager, meanwhile, will focus on protecting IT assets.
“You’ll be able to partition the PC and send patches without having to reboot the machine,” Ward said. “I talked to one CIO who said his firm loses US$1 million in productivity every time a virus hits them.”
As it moves to dual-core chips, Intel will also be changing its fabrication process. While more Intel chips are now being manufactured from 90 nm wafers, Otellini said a 65 nm process, which would double the number of transistors per area, would be in place by the third quarter of next year.