Intel plans 90-nanometre process for Pentium M

SAN JOSE, Calif. — A new generation of the Intel Pentium M processor for mobile computers based on 90-nanometre technology will ship before the end of the year, according to Anand Chandrasekher, vice-president and general manager of the company’s

mobile platforms groups.

Code-named Dothan, the next-generation Pentium M will pack 140 million transistors and two megabytes of cache onto an 87-square-millimetre die.

Intel director of process architecture and integration Mark Bohr told a press briefing earlier in the week at the fall Developer’s Forum that yields of 300 mm wafers of 90-nm processors are now high enough to be built in volume. Intel has six plants geared for 300-mm wafer fabrication. One in Oregon and another in New Mexico are running. A second Oregon plant and one in Ireland are due to come on line next year, and two Arizona plants will be converted to produce 300-mm wafers.

The 135-nm transistor was the transition generation from 200-mm to 300-mm production for Intel, Bohr said.

Transistor sizes have become 70 per cent the size of the previous generation every two years, from 180 nms in 1999 to 130 in 2001. But gate sizes have got smaller at an even faster rate.

The gate length of the 90-nm transistors is 50 nms — smaller than a flu virus.

The new transistors are the first to use strained silicon, in which the distance between atoms is slightly stretched, allowing for faster electron flow, says Bohr. He equated the 10- to 20-per cent performance increase to half a generation’s improvement.

The new transistors feature nickel silicide caps, whose resistance decreases at smaller gate lengths, while traditional cobalt silicide’s increases, says Bohr.

Interconnects are built with seven layers of copper and one of low-k carbon doped oxide, which Bohr said reduces capacitance by 20 per cent for faster interconnection.

Transistor sizes haven’t bottomed out, according to Sunlin Chou, Intel’s senior vice-president and general manager of the technology and manufacturing group. We’ll see 65-nm transistors with 30-nm gates in 2005, with sizes decreasing every two years until 2011 produces a 22-nm transistor with a 10-nm gate.

As transistors get smaller, though, current leakage becomes a problem. To go as small as 45 nm, transistors will have to be built in 3-D — a much more complicated build. However, says Chou, “”We think it’s manufacturable.””

Chou said the limits to how small transistors can be change with the technology. When a 3-D structure is no longer adequate, transistors will be made smaller by creating them from carbon nanotubes and silicon nanowire.

“”It’s part of our normal, ongoing business to make devices smaller,”” Chou said.

Other IDF developments:

  • Intel launched the 855GME chipset, which incorporates power management technology that dims the backlighting of laptop screens dynamically, reducing current draw from five watts ti three watts in a demonstration.
  • The Sonoma mobile platform will launch in the second half of next year, building on Centrino mobile technology. It will incorporate 802.11.a/b/g WiFi capability, a new chipset and graphics engine and support for PCI Express and ExpressCard peripherals.
  • A future Xscale processor, code-named Bulverde, will use wireless MMX technology to allow a better gaming experience and the recording, compression and decompression of audio and video on cell phones and PDAs. ETA is late 2004.

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Dave Webb
Dave Webb
Dave Webb is a technology journalist with more than 15 years' experience. He has edited numerous technology publications including Network World Canada, ComputerWorld Canada, Computing Canada and eBusiness Journal. He now runs content development shop Dweeb Media.

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